1/4 rev. a structure silicon monolithic integrated circuit name of product dc-ac inverter control ic type ?? function ?2ch control with push-pull ?lamp current and voltage sense feed back cont rol ?sequencing easily achieved with soft start control ?short circuit protection with timer latch ?under voltage lock out ?short circuit protection with over voltage ?mode-selectable the operating or stand-by mode by stand-by pi n ?synchronous operating the other BD9888F or BD9888Fv ic s ?burst mode controlled by pwm and dc input ?short circuit protection with voltage difference detection absolute maximum ratingsta = 25 parameter symbol limits unit supply voltage v cc 15 v operating temperature range topr -40+90 storage temperature range tstg -55+125 power dissipation pd 600 *1 (BD9888F) mw 850 *2 (BD9888Fv) maximum junction temperature tjmax +125 *1 pd derate at 6.0mw/ for temperature above ta = 25 (when mounted on a pcb 70.0mm70.0mm1.6mm) *2 pd derate at 8.5mw/ for temperature above ta = 25 (when mounted on a pcb 70.0mm70.0mm1.6mm) recommended operating condition status of this document the japanese version of this document is the official specifica tion. please use the translation version of this document as a reference to expedite understanding of the official version. if these are any uncertainty in translation version of this document, official version takes priority. parameter symbol limits unit supply voltage v cc 5.014.0 v ct oscillation frequency f ct 20150 khz bct oscillation frequency f bct 0.050.50 khz
2/4 rev. a electric characteristicsta=25vcc=7v parameter symbol limits unit conditions min. typ. max. whole device operating current icc1 11.0 17.0 ma ct=0.5v stand-by current icc2 2 10 a over voltage detect fb over voltage detect voltage vovf 2.20 2.40 2.60 v stand by control stand-by voltage h vsth 1.6 vcc v system stand-by voltage l vstl -0.3 0.8 v system stand-by hysteresis Svst 0.08 0.18 0.28 v timer latch timer latch voltage vcp 1.9 2.0 2.1 v timer latch current icp 0.5 1.0 1.5 a burst mode bosc max voltage vburh 1.94 2.0 2.06 v f bct =0.2khz bosc min voltage vburl 0.4 0.5 0.6 v f bct =0.2khz bosc constant current i bct 1.35/brt 1 .5/ brt 1.65/brt a bosc frequency f bct 266 280 294 hz brt=33k?bct=0.050f osc block osc constant current i ct 1.35/rt 1.5/rt 1.65/rt a osc max voltage vosch 1.8 2.0 2.2 v f ct =60khz osc min voltage voscl 0.3 0.5 0.7 v f ct =60khz max duty maxduty 44 46.5 49 % f ct =60khz soft start current iss 1.0 2.0 3.0 a is comp detect voltage visc 0.45 0.50 0.55 v ss comp detect voltage vss 2.0 2.2 2.4 v srt on resistance r srt 200 400 uvlo block operating voltage vuvloh 4.100 4.300 4.500 v shut down voltage vuvlol 3.900 4.100 4.300 v reg block reg output voltage v reg 3.038 3.100 3.162 v reg source current i reg 5.0 ma vref voltage v ref 1.225 1.250 1.275 v vref=open feed back block is threshold voltage vis 1.225 1.250 1.275 v vs threshold voltage vvs 1.220 1.250 1.280 v is source current 1 iis1 1.5 a duty=2.0v is source current 2 iis2 13.0 20.0 27.0 a duty=0vis=0.5v vs source current ivs 1.0 a output block nach output voltage h voutnah vcc-0.3 vcc-0.1 v nbch output voltage h voutnbh vcc-0.3 vcc-0.1 v nach output voltage l voutnal 0.1 0.3 v nbch output voltage l voutnbl 0.1 0.3 v nach output sink resistance rsinkna 5 10 isink = 10ma nach output source resistance rsourcena 8 16 isource = 10ma nbch output sink resistance rsinknb 5 10 isink = 10ma nbch output source resistance rsourcenb 8 16 isource = 10ma drive output frequency f out 58.5 60.0 61.5 khz rt=18k?ct=395pf comp block under voltage detect v comp l 0.620 0.640 0.660 v voltage difference detect Sv comp 0.40 0.45 0.5 v |v comp a-v comp b| this product is not designed to be radiation-resistant.
3/4 rev. a package dimensions block diagram pin description pin no. pin name function 1 duty control pwm mode and burst mode 2 brt external resistor from brt to gnd for adjusting the burst triangle oscillator 3 bct external capacitor from bct to gnd for adjusting the burst triangle oscillator 4 rt external resistor from srt to rt for adjusting the triangle oscillator 5 srt external resistor from srt to rt for adjusting the triangle oscillator 6 ct external capacitor from ct to gnd for adjusting the triangle oscillator 7 gnd ground 8 fb1 error amplifier output 9 is1 error amplifier input 10 vs1 error amplifier input 11 fb2 error amplifier output 12 is2 error amplifier input 13 vs2 error amplifier input 14 vref reference voltage 15 compa1 voltage difference or under voltage detect for 1ch 16 stb stand-by switch 17 compb1 voltage difference or under voltage detect for 1ch 18 compa2 voltage difference or under voltage detect for 2ch 19 compb2 voltage difference or under voltage detect for 2ch. 20 reg internal regulator output 21 ss external capacitor from ss to gnd for soft start control 22 scp external capacitor from scp to gnd for timer latch 23 na2 fet driver for 2ch 24 nb2 fet driver for 2ch 25 pgnd ground for fet drivers 26 nb1 fet driver for 1ch 27 na1 fet driver for 1ch 28 vcc supply voltage input BD9888Fv BD9888F lot no. device mark (include burr 10.35 ) (include burr 18.85 ) ssop-b28 (unit:mm) sop28 (unit:mm) stb block systemon/off osc bosc ct vcc rt brt bct duty na1 nb1 stb is1 duty block reg block uvlo block vcc reg vref f/b block pwm block logic block output block ss ct vs1 ss fb1 na2 nb2 is2 f/b block pwm block logic block output block ss ct vs2 fb2 protect block gnd pgnd scp srt vcc vcc comp block voltage difference detect block voltage difference detect block compa1 compb1 compa2 compb2
4/4 rev. a p substrate parasitic diode gnd n p p resistance transistor (npn) other adjacent components parasitic diode (pinb) (pina) p gnd p substrate gnd n n b c e n n (pina) (pinb) parasitic diode gnd gnd parasitic diode c b e note for use . when designing the external circuit, including adequate margins for variation between external devices and ic. use adequate margins for steady state and transient characteristics. . the circuit functionality is guaranteed within of ambient temperature operation range as long as it is within recommended operating range. the standard electrical characteristic values cannot be guaranteed at other voltages in the operating ranges, however the variation will be small. . mounting failures, such as misdirection or miscounts, may harm the device. . a strong electromagnetic field may cause the ic to malfunction. . the gnd pin should be the location within 0.3v compared with the pgnd pin. . BD9888F and BD9888Fv incorporate a built-in thermal shutdown circuit (tsd circuit). the thermal shutdown circuit (tsd circuit) is designed only to shut the ic off to prevent runaway thermal operation. it is not designed to protect the ic or guarantee its operation of the thermal shutdown circuit is assumed. . absolute maximum ratings are those values that, if exceeded, may cause the life of a device to become significantly shortened. moreover, the exact failure mode caused by short or open is not defined. physical countermeasures, such as a fuse, need to be considered when using a device beyond its maximum ratings. . about the external fet, the parasitic capacitor may cause the gate voltage to change, when the drain voltage is switching. make sure to leave adequate margin for this ic variation. . on operating slow start control (ss is less than 2.2v), it does not operate timer latch. . by stb voltage, BD9888F and BD9888Fv are changed to 2 states. therefore, do not input stb pin voltage between one state and the other state (0.81.6). . the pin connected a connector need to connect to the resistor for electrical surge destruction. this ic is a monolithic ic which (as shown is fig-1) has p + substrate and between the various pins. a p-n junction is formed from this p layer of each pin. for example, the relation between each potential is as follows, (when gnd > pinb and gnd > pina, the p-n junction operates as a parasitic diode.) (when pinb > gnd > pina, the p-n junction operates as a parasitic transistor.) parasitic diodes can occur inevitably in the structure of the ic. the operation of parasitic diodes can result in mutual interference among circuits as well as operation faults and physical damage. accordingly you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than the gnd (p substrate) voltage to an input pin. this ic is a monolithic ic which (as shown is fig-1)has p + substrate and between the v arious pins. a p-n junction is formed from this p layer of each pin. for example, the relation between each potential is as follows, (when gnd > pinb and gnd > pina, the p-n junction operates as a parasitic diode.) (when pinb > gnd > pina, the p-n junction operates as a parasitic transistor.) parasitic diodes can occur inevitably in the structure of the ic. the operation of parasitic diodes can result in mutual interference among circuits as well as operation faults and physical damage. accordin gly you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than the gnd (p substrate) voltage to an input pin. fig-1 simplified structure of a bipolar ic
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